Performance enhancement between generations of integrated circuit devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling”. As scaling increases, to achieve faster device speeds using transistor IC technology, shorter gate lengths, thinner gate oxides and faster response times are necessary.
Metal-oxide-Semiconductor-Field-Effect-transistors, MOSFETs, having a source, a drain region, and a gate electrode formed using a gate oxide, are commonly used in IC devices. As the gate oxide becomes thinner, the device must be powered with a lower voltage power supply to avoid breakdowns and leakage.
Additionally, as CMOS on bulk silicon devices are scaled to channel lengths below 100 nm, conventional CMOS devices suffer from several problems. For example, conventional planar complementary metal oxide semiconductor (CMOS) technology on bulk silicon having a short gate length or node, such as 90 nm or 65 nm, suffers from a degraded performance, including increased leakage currents that occur through channels, junctions, and gate dielectrics. In particular, interactions between the source and drain of the CMOS device typically results in both Vt roll-off and sub-threshold swing, degrading the ability of the gate of the device to control whether the device is on or off. This phenomenon is typically referred to as the “short-channel effect”.
To overcome the degraded performance of CMOS on bulk silicon, FinFET transistors on silicon-on-insulator (SOI) structures may be used. Several embodiments of FinFET transistors on SOI structure are disclosed in detail in Hu, (U.S. Pat. No. 6,413,802 B1, issued on Jul. 2, 2002 which is herein incorporated by referenced.
In the generation of layouts for electronic devices, FET can typically be defined by a silicon active area that-intersects with one or more polysilicon lines. The silicon active area is often a two-dimensional, planar layer of silicon. Recent advances allow the planar layer to be replaced by a three-dimensional layer of silicon to create what is commonly referred to as a FinFET.
Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide) below the device active region, unlike conventional “bulk” MOSFETs, which are formed directly on silicon substrates, and hence, have silicon below the active region. The use of SOI MOSFETs increases device speed over that of CMOS on bulk through smaller subthreshold voltage swings (i.e. better switching off performance). Additionally, SOI MOSFETS are advantageous since the SOI MOSFET reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel as well as each other. As device size is scaled, however, this becomes increasingly difficult, since the distance between the source and drain is reduced, and hence, both the source and the drain increasingly interact with the channel, thus reducing gate control and increasing short channel effects (SCE).
As shown in prior art FIGS. 1-2a-d, 3-5, a conventional FinFET on SOI structure 10 has a double-gate (DG) MOSFET device that has a thin channel or “fin” region disposed on a SOI. The fin 12 is a silicon shape built on a silicon 14 or Silicon On Insulator (SOI) substrate 16, and extends vertically out of the plane of the substrate to build FET structures. The vertical sides of the fin can be utilized to form FETs. These FETs incorporated into fin structures are called FinFETs.
Among many DG MOS SOI structures, the FinFET structure on SOI has at least one thin vertical fin 12 and self-aligned double gates 18 “wrapped around” or over both sides of the at least one thin vertical fin 12. The DG MOSFET SOI structure 10 provides gate control of the fin from both sides of the fin, thereby reducing SCE. The “wraparound gate” 18 places a gate so that it completely or almost-completely surrounds the fin 12 or channel and thus, provides better gate control and enhances drive currents.
Preferably, the thin fin 12 is made of a silicon material and has the gate overlying the edges of the fin. Alternatively, a wider channel transistor 19 may be formed by providing multiple fins 21 in parallel to share a common gate 23, as shown in FIG. 5.
Both the DG CMOS on SOI device of prior art FIGS. 1, 2a-d, and 3-5 have demonstrated superior performance over planar CMOS on bulk silicon devices by providing both suppression of short-channel effects and reducing leakage currents.
The conventional DG MOSFET on SOI structure is fabricated in a similar manner to that of a planar CMOS on bulk silicon device. Prior art FIG. 1 is an illustration of a FinFET transistor on SOI having one silicon fin. The fin 12 has a thickness of about 15 nm can be formed using existing technology such as e-beam lithography. However, the throughput of E-beam lithography is low and the uniformity is not satisfactory for a sub-30 nm gate length device. Uniformity is critical for a FinFET device because a variation in a fin thickness can cause a change in the channel potential and subband structure, which governs short-channel behavior and quantum confinement effects.
In general, the width, or thickness of each silicon fin ranges between 15 to 40 nm. Additionally, the height of the fin ranges between 45 to 100 nm. The height-to-width ratio or “aspect ratio” of the fin, approximately three-to-one, is higher than that of a planar CMOS fabrication process.
The FinFET on SOI structure shown in prior art FIGS. 1, 2a-d and 3-5 has superior features over planar CMOS on bulk including excellent gate control and elimination of electrostatic coupling and leakage of current between the source and the drain.
The gate wrapping over two side-walls of the vertical un-doped fin of the FinFET on SOI structure provides excellent gate control for turn-off performance, and for turn-on performance by providing the well-known “thin-body” effects, e.g. enhanced mobility and volume immersion. In general, all of the thin fins have the same thickness, and wider transistors may be formed by providing parallel multi-fins that share a common gate (see FIG. 5).
Electrostatic coupling and leakage of both the source and the drain through the bulk silicon is eliminated by using a buried oxide (BOX) layer 16 disposed beneath the device active area.
As shown in FIGS. 2a-d, the fabrication of FinFET on SOI is similar to that of conventional planar CMOS fabricated on bulk silicon as is well known by a person of ordinary skill in the art.
Prior art FIGS. 2a-d illustrate the conventional process of fabricating a FinFET on SOI structure.
FIG. 2a shows Fin patterning and Vt implanting. The silicon layer (un-doped) is formed first by fine lithography (e.g. e-beam) 24 and then is further formed by silicon etching and followed by a Vt implant. As shown in FIG. 2a, the step of Vt implant after silicon etching is optional depending on which gate conduction materials are used.
Unlike bulk substrate fabrication, formation of a shallow trench isolation (STI) trench is not necessary because isolation is provided by the buried oxide layer of SOI.
As shown in FIG. 2b, after the fin patterning process is performed, the surface of the fin is oxidized to form a gate oxide (GOX). Next, after gate oxidation, a gate conductor film, preferably selected from at least one of poly-Si, Mo, and TiN, is deposited over the silicon fin and is patterned as the gate conductor 18. Preferably, the gate is patterned by using an etching process to form perfectly aligned gates straddling over the two sidewalls of the patterned fin. The resulting channel width is calculated to be about 2 times the fin-height associated with each fin, wherein the fin-height is the thickness of the silicon layer of the FinFET on SOI structure.
The threshold voltage, Vt, of the device may be controlled by adjusting the work function of the gate conduction material using a refractory metal, a compound such as titanium nitride, or an alloy such as silicon-germanium alloy. The Vt is determined as is well-known in the art by using a work function of the gate conduction material and a density value of carriers at an on-state.
FIG. 2c illustrates a selective implantation of a lightly doped drain (“LDD”) region using a large tilt angle implant 28 into the selective surface of the substrate, thus providing uniformity. The arrows in different angles in FIG. 2c schematically represent the “large angle tilting” during implanting. The photo resist 20 pattern is formed by a typical masking step. The selective LDD implant is therefore performed for n-channel and p-channel regions respectively.
As shown in FIG. 2d, a spacer 30 is formed on the sidewall of the gate 18 and the fin or channel 12 by deposition and etch-back technique. The spacer material is typically silicon dioxide or silicon nitride.
After the spacer is formed, the silicon portion of the fin is exposed (i.e. the portion not underneath the gate and the spacer) to form the source and the drain by heavy n+ or P+ implant using masking steps (not shown in FIG. 2d).
FIG. 3 shows a top view of a FinFET device shown in FIG. 2d having a mask 34 formed thereon (gate 18 not shown). The resistance of the source and drain can be reduced by forming a mask or passivation layer 34 on the source and the drain regions. The passivation layer 34 is formed by depositing a conductive material on the source region, and the drain region. The conductive material may be a metallic silicide such as titanium silicide, cobalt silicide, or nickel silicide, a metallic nitride such as titanium nitride and tantalum nitride, a metal such as tungsten ad copper, or a heavily doped semiconductor such as n+ doped Si.
If the conductive material is cobalt silicide, it may be formed by a self-aligned suicide (salicide) process. In the source and drain regions, the conductive material may be formed on both the top of the fin as well as the sidewall of the fin.
Finally, as shown in FIG. 4, contacts 36 are formed on the conductive material mask between the source, and drain regions using techniques well-known in the art (gate 18 not shown).
SOI technology further improves the speed at which transistors perform and reduces the voltages required to power the transistor. The SOI layer not only reduces the capacitance of the semiconductor switch so it operates faster, but also eliminates the “body effect” which causes lower current and lower performance in CMOS on bulk technology. Due to the SOI characteristics, the FinFET on SOI can operate at lower power than CMOS on bulk technology.
However, narrow fin widths can cause high channel resistance in DG FinFET on SOI devices. It is important to have a very low contact resistance in nanoscale devices.
Therefore, it an object of the present invention to reduce the high channel resistance in DG FinFET on SOI devices having narrow fin widths.
It is a further object of the present invention to eliminate the need for a top mask or passivation layer on top of the source and drain regions of a FinFET transistor device.